-- This component contains the xmt_port_monitor and the SF_fifo2xmt_interface 
-- The SF_fifo2xmt contains: SF_FIFO_monitor and the Counter C (contains Counter B)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SF_fifo2xmt_interface is 
  port(
	reset, clk: in std_logic;
	ODL_emp: 	in std_logic_vector (2 downto 0);	-- monitors SF FIFOs
	i_D_FIFO: 	in std_logic_vector (7 downto 0);   -- input from 8 bit Data FIFO
	i_L_FIFO: 	in std_logic_vector (11 downto 0);  -- input from 12 bit Length FIFO
	i_O_FIFO: 	in std_logic_vector (3 downto 0);   -- input from 3(now 4 bits) bit Output Port FIFO
	rd_D_FIFO, rd_L_FIFO, rd_O_FIFO: out std_logic;	-- read requests for Data, Length, and output FIFOs
	o_D_xmt: 	out std_logic_vector (7 downto 0);  -- out to xmt D FIFOs
	o_L_xmt: 	out std_logic_vector (11 downto 0); -- out to xmt L FIFOs
		--pins for testing internal coutner
--	count_test: out std_logic_vector (11 downto 0); 
		--control path inputs from xmt port
	xmt_wordsused0, xmt_wordsused1: in std_logic_vector (12 downto 0);
	xmt_wordsused2, xmt_wordsused3: in std_logic_vector (12 downto 0);
		--data path outputs to xmt port
	w_xTest: out std_logic_vector (3 downto 0);
	xmt_dwtreq, xmt_lwtreq: out std_logic_vector (3 downto 0)
    );
    
end SF_fifo2xmt_interface; 

architecture main of SF_fifo2xmt_interface is 
-------------------------------------------
component counter_fifo_monitor_merger is
  port(
	reset, clk: in std_logic;
	ODL_emp: 	in std_logic_vector (2 downto 0);	    -- monitors SF FIFOs
	i_L_FIFO: 	in std_logic_vector (11 downto 0);    -- input from 12 bit Length FIFO
	i_O_FIFO: 	in std_logic_vector (3 downto 0);     -- input from 3 (now 4) bit Output Port FIFO
	rd_D_FIFO, rd_L_FIFO, rd_O_FIFO: out std_logic;	--read requests for Data, Length, and output FIFOs
	o_xLF: 		out std_logic_vector(11 downto 0); 	    -- 12 bit Length output, connected to each xmit L FIFO
	w_xLF: 		out std_logic_vector (3 downto 0);	    -- 4 bit output to write request, one for each xmit L FIFO 
	w_xDF: 		out std_logic_vector(3 downto 0)	    -- 4 bit output to write request, one for each xmit L FIFO
    );
end component; 

component xmt_port_monitor is
	port(
		reset, clk: in std_logic;
		
		--control path inputs from xmt port
		xmt_wordsused: in std_logic_vector(12 downto 0);
		
		--control path inputs from SF_xmt_interface
		SF_PacketComing, SF_PacketFinished: in std_logic;
		SF_PacketLength: in std_logic_vector(11 downto 0);
		
		--data path inputs from SF_xmt_interface
		SF_dwtreq, SF_lwtreq: in std_logic;
		
		--data path outputs to xmt port
		xmt_dwtreq, xmt_lwtreq: out std_logic
	);
end component;
-------------------end of components-----------------------------------------------------
-------------------declare signals-------------------------------------------------------
		--outputs from SF_xmt_interface to xmt_port_monitor
  	signal s_o_xLF: std_logic_vector(11 downto 0);  -- 12 bit Length output, connected to each xmit L FIFO
	signal s_w_xLF: std_logic_vector (3 downto 0);	-- 4 bit output to write request, one 4 each xmit L FIFO 
	signal s_w_xDF: std_logic_vector(3 downto 0);	-- 4 bit output to write request, one 4 each xmit D FIFO
			--outputs from SF_xmt_interface to FIFOs
	signal s_rd_D_FIFO, s_rd_L_FIFO, s_rd_O_FIFO: std_logic;

			--control path inputs from xmt port
	signal s_xmt_wordsused0, s_xmt_wordsused1: std_logic_vector (12 downto 0);
	signal s_xmt_wordsused2, s_xmt_wordsused3: std_logic_vector (12 downto 0);
			--data path outputs to xmt port
	signal s_xmt_dwtreq, s_xmt_lwtreq: std_logic_vector (3 downto 0);	

-------------------end of signal declarations--------------------------------------------	


begin
-------------------begin port mapping ---------------------------------------------------
SF_xmt_interfaceA: counter_fifo_monitor_merger
	port map(	
	clk=>clk, 			
	reset=>reset, 
	ODL_emp		=>	ODL_emp, 		--monitors FIFOs, when all are zero, process starts
	i_L_FIFO	=>	i_L_FIFO,		--12bit Length Value from FIFO
	i_O_FIFO	=>	i_O_FIFO,		--3 (now 4) bit Data Value from FIFO
	rd_D_FIFO	=>	s_rd_D_FIFO, 	--rd signal to Data FIFO
	rd_L_FIFO	=>	s_rd_L_FIFO, 	--rd Signal to Length FIFO
	rd_O_FIFO	=>	s_rd_O_FIFO, 	--rd signal to Output FIFO 
	o_xLF		=>	s_o_xLF, 		--Length value output to xmt_length FIFOs
	w_xLF		=>	s_w_xLF, 		-- write signals to xmt Length FIFOs
	w_xDF		=>	s_w_xDF			--write signals to xmt Data FIFOs
	);
	
xmt_port_monitor0: xmt_port_monitor
	port map(
		clk					=>	clk, 			
		reset				=>	reset, 
			--control path inputs from xmt port
		xmt_wordsused		=> s_xmt_wordsused0,
		
			--control path inputs from SF_xmt_interface
		SF_PacketComing		=> 	s_rd_O_FIFO, 
		SF_PacketFinished	=>	s_w_xLF(0), 
		SF_PacketLength		=>	i_L_FIFO, --s_o_xLF,
		
			--data path inputs from SF_xmt_interface
		SF_dwtreq			=>	s_w_xDF(0), 
		SF_lwtreq			=>	s_w_xLF(0),
		
			--data path outputs to xmt port
		xmt_dwtreq			=>	s_xmt_dwtreq(0), 
		xmt_lwtreq			=>	s_xmt_lwtreq(0)
	);
xmt_port_monitor1: xmt_port_monitor
	port map(
		clk					=>	clk, 			
		reset				=>	reset, 
			--control path inputs from xmt port
		xmt_wordsused		=>	s_xmt_wordsused1,
		
			--control path inputs from SF_xmt_interface
		SF_PacketComing		=> 	s_rd_O_FIFO, 
		SF_PacketFinished	=>	s_w_xLF(1), 
		SF_PacketLength		=>	i_L_FIFO, --s_o_xLF,
		
			--data path inputs from SF_xmt_interface
		SF_dwtreq			=>	s_w_xDF(1), 
		SF_lwtreq			=>	s_w_xLF(1),
		
			--data path outputs to xmt port
		xmt_dwtreq			=>	s_xmt_dwtreq(1),
		xmt_lwtreq			=>	s_xmt_lwtreq(1)
	);	
	
xmt_port_monitor2: xmt_port_monitor
	port map(
		clk					=>	clk, 			
		reset				=>	reset, 
			--control path inputs from xmt port
		xmt_wordsused		=>	s_xmt_wordsused2,
		
			--control path inputs from SF_xmt_interface
		SF_PacketComing		=> 	s_rd_O_FIFO,
		SF_PacketFinished	=>	s_w_xLF(2), 
		SF_PacketLength		=>	i_L_FIFO, --s_o_xLF,
		
			--data path inputs from SF_xmt_interface
		SF_dwtreq			=>	s_w_xDF(2), 
		SF_lwtreq			=>	s_w_xLF(2),
		
			--data path outputs to xmt port
		xmt_dwtreq			=>	s_xmt_dwtreq(2), 
		xmt_lwtreq			=>	s_xmt_lwtreq(2)
	);	
	
xmt_port_monitor3: xmt_port_monitor
	port map(
		clk					=>	clk, 			
		reset				=>	reset, 
			--control path inputs from xmt port
		xmt_wordsused		=>	s_xmt_wordsused3,
		
			--control path inputs from SF_xmt_interface
		SF_PacketComing		=> s_rd_O_FIFO, 
		SF_PacketFinished	=>	s_w_xLF(3), 
		SF_PacketLength		=>	i_L_FIFO, --s_o_xLF,
		
			--data path inputs from SF_xmt_interface
		SF_dwtreq			=>	s_w_xDF(3), 
		SF_lwtreq			=>	s_w_xLF(3),
		
			--data path outputs to xmt port
		xmt_dwtreq			=>	s_xmt_dwtreq(3), 
		xmt_lwtreq			=>	s_xmt_lwtreq(3)
	);	
	
-----------------------------------
		--outputs to FIFOs
	rd_D_FIFO		<=	s_rd_D_FIFO;
	rd_L_FIFO		<=	s_rd_L_FIFO; 
	rd_O_FIFO		<=	s_rd_O_FIFO;
	o_D_xmt 		<= 	i_D_FIFO;
	o_L_xmt 		<= 	s_o_xLF;  -- proble is right here I need lengh value asserted. 
		--output for testing counter
--	count_test			<=s_count_test;
		--control path inputs from xmt port
	s_xmt_wordsused0	<= 	xmt_wordsused0;
	s_xmt_wordsused1	<= 	xmt_wordsused1;
	s_xmt_wordsused2	<= 	xmt_wordsused2;
	s_xmt_wordsused3	<= 	xmt_wordsused3; 
		--data path outputs to xmt port
	xmt_dwtreq			<=	s_xmt_dwtreq;  --s_w_xDF; --s_xmt_dwtreq;
	xmt_lwtreq			<=	s_xmt_lwtreq;  --s_w_xLF; --s_xmt_lwtreq;
	w_xTest 			<= 	s_w_xDF;
end main;